1. Field of the Invention
The present invention relates to an electronic system and, more particularly, to a frequency modulator that can synthesize fractional-N frequency output using multiple vectors chosen to lower output jitter and increase selectivity and resolution of the fractional output.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art or conventional by virtue of their inclusion within this section.
Within nearly every electronic subsystem is some form of generator that produces cyclical waveforms. The waveform generator is oftentimes referred to as an oscillator. Oscillators can be rated depending on their stability and accuracy, frequency adjustability (i.e., tunability), and power consumption. The output from an oscillator is referred to as the reference frequency Fx. This reference frequency can thereafter be tuned using, for example, a phase-locked loop (PLL). Usually FX is too high so the incoming signal is usually first divided down Q times by a reference frequency divider and becomes the reference frequency FR for the phase frequency detector (PFD). Thus, FR=FX/Q. The PLL then employs a divider within its feedback loop to selectively increase the PFD's reference frequency FR. The resonator output frequency can be tuned using what will henceforth be referred to as a “frequency synthesizer.”
There are numerous ways in which to design a frequency synthesizer using a PLL. For example, the divider within the feedback loop of the PLL can be modified in integer increments. Thus, output from the frequency synthesizer will be in integer-N multiples of the reference frequency FR. In a traditional PLL implementation, the output will be represented as the voltage-controlled oscillator output, and will transition at a frequency of FVCO. Thus, FVCO=N*FR=N/Q*FX. An unfortunate aspect of integer-N frequency dividers is that the selectable discrete frequencies of FVCO is dependent on the value of N. The frequency spacing, oftentimes referred to as the minimum frequency resolution, or minimum channel spacing, using an integer-N divider can, in some instances, be too high for an intended application. Another issue is that for some applications, the integer N must be very large, and results in high phase noise.
Given that frequency synthesizers are used in a wide variety of applications, including FM radios, radar systems, cellular and PCS telephone systems, test equipment such as spectrum analyzers and signal generators, it would be desirable to implement a frequency synthesizer having a smaller minimum channel spacing. In order to achieve a smaller minimum channel spacing, fractional-N dividers are needed. In addition to achieving smaller channel spacing, fractional-N dividers allow small divide values to achieve the same channel spacing, which reduces the phase noise.
A fractional-N divider within the feedback loop can produce a synthesizer output of FVCO=FR(N+n/d). Thus, in addition to the integer divide factor N, a fractional-N divider will introduce fractions between integers set by a numerator value (n) divided by a denominator value (d). For example, when d=8, n may be an integer from 0 to 7. This example will increase the integer PLL resolution by a factor of 8 by adding 7 divide values between N and N+1. Thus the channel spacing is ⅛ of an integer PLL.
A fractional-N divider usually comprises a fractional-N control logic circuit and an integer-N divider. The divide value of the integer-N divider is switched between two integer values in a manner set by the fractional-N control logic circuit. Thus the average divide value is a fractional number. The way a fractional-N divider works causes signal spurs that are not usually seen on an integer divider, because each time the divide value changes, the PLL makes an abrupt phase correction. To minimize the spurs, the sequence of divide value should be carefully selected. One approach is delta-sigma modulation. To meet even higher performance requirement, compensation circuits should be used to cancel the signal spurs.
Therefore, a fractional-N divider is one that divides the reference frequency by a mixed number containing a fraction in order to achieve a synthesized frequency at the output of the PLL. A pattern of values are fed to the divider, and that pattern represents a modulated output. The output is typically modulated around two values. For example, if the fractional-N divider is 50.125, then the majority of the sequential pattern will be of 50 value with a periodic 51 value interspersed within the pattern. The number of 50 values to the number of 51 values is quite large. Using this example, a 51 value appears rarely in relation to 50 values within the modulated string or sequence of values. A low frequency spur may therefore arise, and cannot be easily removed by the low-pass filter of the PLL. This low frequency occurrence within the modulated output will produce substantial jitter in the pass band of the synthesized frequency.
It would be desirable to introduce a modulator and frequency synthesizer circuit that avoids low frequency jitter by giving greater selectivity to the modulated pattern input to the PLL divider. A lower jitter-producing pattern may be one that can beneficially achieve higher resolution for the average divide value, as well as providing an average divide value that can be substantially near an integer value. An improved modulator output is thereby one that can achieve high resolution changes in the average divide value, yet more often (and with higher frequency) modulate changes at that output. The higher frequency changes are more effectively removed by the low-pass filter of the PLL.